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The H5TC1G43TFR-xxA and H5TC1G83TFR-xxA are a 1Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.)

Hynix 1Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.


  • VDD=VDDQ=1.35V + 0.100 / - 0.067V
  • Fully differential clock inputs (CK, /CK) operation
  • Differential Data Strobe (DQS, /DQS)
  • On chip DLL align DQ, DQS and /DQS transition with CK transition
  • DM masks write data-in at the both rising and fallingedges of the data strobe
  • All addresses and control inputs except data,data strobes and data masks latched on the rising edges of the clock
  • Programmable CAS latency 6, 7, 8, 9, 10 supported
  • Programmable additive latency 0, CL-1, and CL-2 supported
  • Programmable CAS Write latency (CWL) = 5, 6, 7
  • Programmable burst length 4/8 with both nibblesequential and interleave mode
  • BL switch on the fly
  • 8banks
  • Average Refresh Cycle(Tcase of 0 oC~ 95 oC)
    - 7.8 As at 0oC ~ 85 oC
    - 3.9 As at 85oC ~ 95 oC
  • Auto Self Refresh supported
  • JEDEC standard 78ball FBGA(x4/x8)
  • Driver strength selected by EMRS
  • Dynamic On Die Termination supported
  • Asynchronous RESET pin supported
  • ZQ calibration supported
  • TDQS(Termination Data Strobe) supported (x8 only)
  • Write Levelization supported
  • 8 bit pre-fetch
  • This product in compliance with the RoHS directive.

Technical Data Sheet

Technical Data Sheet
Part Number Rev. Update Date Remark
H5TC1G43TFR 0.1 2010-01-22  

Simulation Model

Simulation Model
Part Number Rev. Update Date Remark
IBIS 1.0 2010-04-22  
Verilog 1.3 2010-05-28  
HSpice 1.0 2010-05-28  

Device Operation

Device Operation
File Name Update Date Remark
DDR3L_device_operation_timing_diagram.pdf 2010-03-04  

Ordering Information